Future intelligent power ICs will require high-density power devices along with analog functions and VLSI logic. DMOS transistors are important in power device applications capable of handling high voltages. For such devices, one figure of merit is the current handling capacity per unit area or the ON resistance per unit area. For a given voltage rating, the ON resistance per unit area may be reduced by reducing the cell area of the MOS device.
In the field of power transistors, the combined width of the polycrystalline silicon (polysilicon) and the contact region, which forms the gate and source electrode, respectively, is defined as the cell pitch of the device. For a DMOS power transistor, a known technique to reduce the width of the polysilicon region is to decrease the P-well junction depth. However, minimum junction depth is defined by the breakdown voltage required.
A conventional structure Lateral DMOS (LDMOS) device is well suited for incorporation into VLSI processes because of its simplicity. However, LDMOS devices have been considered inferior to Vertical DMOS (VDMOS) devices, and therefore have not received significant attention. Recently, a RESURF (Reduced SURface Field) LDMOS device with good specific on-resistance (R.sub.sp) has been demonstrated. But that device structure is more complex and not very versatile, being limited to grounded source applications.
More specifically, in the past, DMOS transistors have been utilized either as discrete power transistors or as components in monolithic integrated circuits. DMOS transistors are inherently conservative of semiconductor substrate area because of the manner in which they are fabricated in a self-aligned fabrication sequence.
A channel body region is usually first formed by dopant introduction of one type dopant (P or N impurities) through an aperture in a mask of gate-forming material to provide a channel region which is self-aligned with the gate. Then a source region is usually formed by dopant introduction of a type opposite to that of the channel body region through the existing aperture so that the source is self-aligned to both the gate electrode and the channel body region. This permits a very compact structure.
Referring to FIG. 1, an LDMOS transistor device 10 of the prior art is illustrated. The device 10 includes two lateral double diffused metal oxide semiconductor (LDMOS) transistors 10a and 10b. The transistor device 10a is formed on a semiconductor-on insulator (SOI) substrate which has a silicon substrate 11, a buffer oxide layer 12 and a semiconductor layer 14. The semiconductor layer 14 is illustrated as overlying the silicon substrate 11. The field effect transistor of the conventional device comprises an N-type source region 16a and a drain region 18a. The source region 16a is formed in a well region 20 of P-type conductivity. The well region 20 is often referred to as a P-type body region. The P-type body region 20 can extend through the layer 14 to an upper surface of the buffer oxide 12 or, alternatively, the body region 20 can be fully within the layer 14 as illustrated.
The drain region 18a is adjacent to the other end of the field insulating region 23a. The field insulating region 23a comprises oxide such as thermally grown silicon dioxide, for example. A gate electrode 26a is also formed over the surface of layer 14. The gate electrode 26a extends from over a portion of the source region 16a to over a portion of the field insulating region 23a. The gate electrode 26a may comprise a layer of doped polysilicon. The gate electrode 26a is separated from the surface of layer 14 by a gate dielectric layer 28a. The gate dielectric layer 28a may comprise a layer of oxide or a layer of nitride or a composite of an oxide layer (O) and a nitride layer (N) (e.g., a stacked NO or ONO layer). Sidewall insulating regions (not shown) may be formed on the sidewalls of gate electrode 26a. The sidewall insulating regions typically comprise an oxide material such as silicon dioxide or a nitride material such as silicon nitride. A more heavily doped body region 30 is also provided in the P-type body region 20. The more heavily doped body region 30 is typically provided to allow good ohmic contact to the P-type body region 20 and is typically more heavily doped than the P-type body 20. Drain and source contacts 32a and 34, respectively, are also included so that electrical contact can be made to the drain and source regions 18a and 16a. In FIG. 1, a single source contact 34 is used for the source regions 16a and 16b of both transistors 10a and 10b. A device similar to the device of FIG. 1 is disclosed in U.S. Pat. No. 5,369,045 to Ng, et al.
Referring now to FIG. 2, another LDMOS transistor device 70 according to the prior art is illustrated. This device 70 includes a silicon substrate 71, typically of N-type silicon material having a constant doping concentration, on which is provided a buried insulating layer 72. The buried insulating layer 72 is typically a silicon oxide layer of between about 0.1 micron and 5.0 microns in thickness. A semiconductor layer 74 such as an N-type silicon layer having a thickness of about 0.3 microns to 3.0 microns, is provided on the buried insulating layer 72. Preferably, the semiconductor layer 74 may have a substantially linearly graded lateral doping profile with a different doping concentration at its left (source) side than at its right (drain) side. A lateral semiconductor device such as an LDMOS transistor, is provided in the semiconductor layer 74. Other types of lateral semiconductor devices that may be provided in the semiconductor layer 74 include lateral insulated-gate bipolar transistors (LIGBT), lateral thyristors and lateral high voltage diodes.
The LDMOS transistor shown in FIG. 2 includes an N-type source region 76 having a high doping concentration therein of greater than 10.sup.15 cm.sup.-3, a P-type channel region 78 having a doping concentration therein at the surface of between 10.sup.16 and 5.times.10.sup.17 cm.sup.-3, and an N-type drain region 80 which has an N-type doping concentration therein of greater than 10.sup.15 cm.sup.-3. In a manner well known to those skilled in the art, a field insulating layer, such as a LOCOS (Local Oxidation of Silicon) oxide layer 82, is provided in and on the semiconductor layer 74 between the source and drain regions. A thinner gate oxide insulating layer 84 is preferably provided over the channel region and a portion of the source region 76. The field insulating layer 82 may typically be about 0.5-2.0 microns thick and the thinner gate oxide may be about 0.03-0.1 microns thick. A gate electrode 86 which may comprise polysilicon is provided on the field insulating layer 82 and the gate oxide 84. The source electrode 88a and the drain electrode 88b which may comprise aluminum or other suitable metal, are also provided over the source and drain regions, respectively.
As illustrated by FIG. 2, the channel region 78 and drain region 80 are electrically coupled by a thin lateral drift region 77 having a substantially linearly graded lateral doping profile as described above. As shown by FIG. 2, the drift region 77 is formed on a portion of the semiconductor layer 74 and is of N-type silicon material. The drift region 77 is covered by the field oxide 82 over the major portion of its length, with a part of the gate electrode 86 covering a major portion of the field oxide 82. The device of FIG. 2 offers excellent high voltage performance, but typically suffers from a number of drawbacks. First, a compromise typically must be made between the obtainable breakdown voltage and on-resistance. Other electrical characteristics, such as thermal conductivity and dielectric constant, are also typically not optimized. A device similar to the device of FIG. 2 is disclosed in U.S. Pat. No. 5,378,912 to Pein.
The devices of FIGS. 1 and 2 typically have a relatively high on-state resistance compared to other LDMOS transistor devices having drift regions with linearly graded doping profiles. This is because the drift region of the conventional LDMOS device is composed of a single doping profile. In order to prevent the withstand voltage from being lowered, it is typically necessary to increase the area of a drift region between the P-type body and the drain contact. However, increasing the area of the drift region typically increases the size of the device and reduces integration levels. In addition, a relatively long duration process step is required to form a heavily doped drain contact region directly in a semiconductor layer because N-type impurity ions of heavy concentration typically have to be diffused into an undoped semiconductor layer. In addition, the drift region of the conventional LDMOS transistor is composed of a semiconductor layer having a single doping profile. Accordingly, if a relatively large drain voltage is applied to the completed LDMOS device, an electric field is concentrated adjacent to the drain region and increases the likelihood of punchthrough and decreases the withstand voltage.